Field
The disclosed embodiments generally relate to clocked memory systems. More specifically, the disclosed embodiments relate to a clocked memory system that supports dynamic bursts to facilitate agile communication between a memory controller and a memory device at varying data loads and improved power efficiency.
Related Art
A portable computing device typically enters a power-saving mode to operate at reduced clock speeds when computational workloads are low. These reduced clock speeds enable the supply voltage to be reduced for rail-to-rail Complementary Metal-Oxide-Semiconductor (CMOS) circuits in the portable computing device, which reduces power consumption and thereby extends battery life. However, link interface circuitry between the processor and the memory as well as analog/mixed-mode circuitry is typically not implemented exclusively in rail-to-rail CMOS and consequently cannot always take full advantage of these speed and voltage reductions. Hence, link/mixed-mode circuitry continues to burn some static power, even though less data is being transferred during the power-saving mode. As a consequence, the power consumed per-bit-transferred by a link can actually increase when the system enters a power-saving mode even though the total power is reduced. In addition, for optimal system power efficiency, most links have a particular operating speed at which they are most power efficient. Ideally the links would, when operational, always be operating at this “sweet spot.”
Hence, what is needed is a method and an apparatus for reducing the power consumption for the link circuitry, roughly proportionally, when a portable computing device enters a power-saving mode that reduces the average data delivery rate.